The present inventive concept herein relates to semiconductor chips and methods of forming the same, and more particularly, to semiconductor chips including a through electrode and methods of forming the same.
Requirements for high reliability, high performance, multi-function, high speed, miniaturization and light weight of products in the electronics industry, such as cell phones, note book computers, etc. have been increasing. In order to satisfy these requirements, studies on semiconductor packages are being performed. Connections between integrated circuits using wire bonding (referred to as two-dimensional connections) may result in high power consumption, design method limitations, signal loss in a wire, etc. Alternatively, a three-dimensional integrated circuit package technique connecting semiconductor chips stacked by a vertical interconnection line has been suggested. The vertical interconnection line connecting the semiconductor chips vertically is referred to as a through silicon via (TSV). The three-dimensional integrated circuit package technique using the through silicon via (TSV) allows for more integrated circuits in the same space and a shorter connection between circuits. Studies to improve reliability and electrical characteristics of semiconductor packages using the three-dimensional integrated circuit package technique including the through silicon via (TSV) have been performed.